| - | units | import_verilog0 | syn0 | floorplan0 | place0 | cts0 | route0 | write_gds0 | write_data0 |
|---|---|---|---|---|---|---|---|---|---|
| errors | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| warnings | 13 | 119 | 41 | 42 | 40 | 40 | 0 | 40 | |
| drvs | --- | --- | --- | 58 | 58 | 68 | --- | 169 | |
| drcs | --- | --- | --- | --- | --- | 0 | --- | --- | |
| unconstrained | --- | --- | 1328 | 1328 | 1328 | 1328 | --- | 1328 | |
| cellarea | um^2 | --- | 2114.581 | 2063.420 | 2223.040 | 2223.040 | 2223.040 | --- | 2223.040 |
| totalarea | um^2 | --- | --- | 5255.510 | 5255.510 | 5255.510 | 5255.510 | --- | 5255.510 |
| utilization | % | --- | --- | 39.262 | 42.299 | 42.299 | 42.299 | --- | 42.299 |
| logicdepth | --- | --- | 0 | 0 | 0 | 0 | --- | 0 | |
| peakpower | mw | --- | --- | 0.002 | 0.002 | 0.002 | 0.002 | --- | 0.002 |
| leakagepower | mw | --- | --- | 0.002 | 0.002 | 0.002 | 0.002 | --- | 0.002 |
| irdrop | mv | --- | --- | --- | --- | --- | --- | --- | 0.098 |
| holdpaths | --- | --- | --- | 0 | 0 | 0 | --- | 0 | |
| setuppaths | --- | --- | --- | 0 | 0 | 0 | --- | 0 | |
| macros | --- | --- | 0 | 0 | 0 | 0 | --- | 0 | |
| cells | --- | 19088 | 18872 | 19403 | 19403 | 19403 | --- | 19403 | |
| registers | --- | 1135 | 1135 | 1135 | 1135 | 1135 | --- | 1135 | |
| buffers | --- | --- | 65 | 596 | 596 | 596 | --- | 596 | |
| inverters | --- | --- | 4758 | 4758 | 4758 | 4758 | --- | 4758 | |
| pins | --- | 550 | 550 | 550 | 550 | 550 | --- | 550 | |
| nets | --- | 23791 | 21947 | 22478 | 22478 | 22478 | --- | 22478 | |
| vias | --- | --- | --- | --- | --- | 144181 | --- | --- | |
| wirelength | um | --- | --- | --- | --- | --- | 48218.000 | --- | --- |
| memory | B | 319.180M | 476.484M | 728.121M | 2.189G | 702.520M | 12.239G | 633.871M | 1.200G |
| exetime | s | 11.269 | 41.380 | 23.870 | 01:35.890 | 32.810 | 01:46.469 | 06.610 | 02:20.539 |
| tasktime | s | 11.816 | 45.087 | 24.984 | 01:36.502 | 33.951 | 01:47.006 | 08.587 | 02:21.578 |
| totaltime | s | 11.816 | 56.903 | 01:21.888 | 02:58.391 | 03:32.342 | 05:19.348 | 05:28.232 | 07:41.223 |
| errors | warnings | drvs | drcs | unconstrained | cellarea | totalarea | utilization | logicdepth | peakpower | leakagepower | irdrop | holdpaths | setuppaths | macros | cells | registers | buffers | inverters | pins | nets | vias | wirelength | memory | exetime | tasktime | totaltime |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 13 | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | 319.180MB | 11.269s | 11.816s | 11.816s |
| errors | warnings | drvs | drcs | unconstrained | cellarea | totalarea | utilization | logicdepth | peakpower | leakagepower | irdrop | holdpaths | setuppaths | macros | cells | registers | buffers | inverters | pins | nets | vias | wirelength | memory | exetime | tasktime | totaltime |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 119 | --- | --- | --- | 2114.581um^2 | --- | --- | --- | --- | --- | --- | --- | --- | --- | 19088 | 1135 | --- | --- | 550 | 23791 | --- | --- | 476.484MB | 41.380s | 45.087s | 56.903s |
| errors | warnings | drvs | drcs | unconstrained | cellarea | totalarea | utilization | logicdepth | peakpower | leakagepower | irdrop | holdpaths | setuppaths | macros | cells | registers | buffers | inverters | pins | nets | vias | wirelength | memory | exetime | tasktime | totaltime |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 41 | --- | --- | 1328 | 2063.420um^2 | 5255.510um^2 | 39.262% | 0 | 0.002mw | 0.002mw | --- | --- | --- | 0 | 18872 | 1135 | 65 | 4758 | 550 | 21947 | --- | --- | 728.121MB | 23.870s | 24.984s | 01:21.888s |
| errors | warnings | drvs | drcs | unconstrained | cellarea | totalarea | utilization | logicdepth | peakpower | leakagepower | irdrop | holdpaths | setuppaths | macros | cells | registers | buffers | inverters | pins | nets | vias | wirelength | memory | exetime | tasktime | totaltime |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 42 | 58 | --- | 1328 | 2223.040um^2 | 5255.510um^2 | 42.299% | 0 | 0.002mw | 0.002mw | --- | 0 | 0 | 0 | 19403 | 1135 | 596 | 4758 | 550 | 22478 | --- | --- | 2.189GB | 01:35.890s | 01:36.502s | 02:58.391s |
| errors | warnings | drvs | drcs | unconstrained | cellarea | totalarea | utilization | logicdepth | peakpower | leakagepower | irdrop | holdpaths | setuppaths | macros | cells | registers | buffers | inverters | pins | nets | vias | wirelength | memory | exetime | tasktime | totaltime |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 40 | 58 | --- | 1328 | 2223.040um^2 | 5255.510um^2 | 42.299% | 0 | 0.002mw | 0.002mw | --- | 0 | 0 | 0 | 19403 | 1135 | 596 | 4758 | 550 | 22478 | --- | --- | 702.520MB | 32.810s | 33.951s | 03:32.342s |
| errors | warnings | drvs | drcs | unconstrained | cellarea | totalarea | utilization | logicdepth | peakpower | leakagepower | irdrop | holdpaths | setuppaths | macros | cells | registers | buffers | inverters | pins | nets | vias | wirelength | memory | exetime | tasktime | totaltime |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 40 | 68 | 0 | 1328 | 2223.040um^2 | 5255.510um^2 | 42.299% | 0 | 0.002mw | 0.002mw | --- | 0 | 0 | 0 | 19403 | 1135 | 596 | 4758 | 550 | 22478 | 144181 | 48218.000um | 12.239GB | 01:46.469s | 01:47.006s | 05:19.348s |
| errors | warnings | drvs | drcs | unconstrained | cellarea | totalarea | utilization | logicdepth | peakpower | leakagepower | irdrop | holdpaths | setuppaths | macros | cells | registers | buffers | inverters | pins | nets | vias | wirelength | memory | exetime | tasktime | totaltime |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | 633.871MB | 06.610s | 08.587s | 05:28.232s |
| errors | warnings | drvs | drcs | unconstrained | cellarea | totalarea | utilization | logicdepth | peakpower | leakagepower | irdrop | holdpaths | setuppaths | macros | cells | registers | buffers | inverters | pins | nets | vias | wirelength | memory | exetime | tasktime | totaltime |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 40 | 169 | --- | 1328 | 2223.040um^2 | 5255.510um^2 | 42.299% | 0 | 0.002mw | 0.002mw | 0.098mv | 0 | 0 | 0 | 19403 | 1135 | 596 | 4758 | 550 | 22478 | --- | --- | 1.200GB | 02:20.539s | 02:21.578s | 07:41.223s |